The present invention is directed, in general to a semiconductor barrier and, more specifically, to a semiconductor barrier for metal-oxide-metal capacitors in sub-0.5 micron CMOS technologies.
Metal-oxide-metal (MOM) capacitors are frequently formed during the manufacture of complementary metal oxide semiconductor (CMOS) devices. One who is skilled in the art is readily aware that a capacitor comprises two conductive surfaces separated by a dielectric. In semiconductor manufacture, MOM capacitors in CMOS devices are commonly formed on a silicon substrate by depositing a first metal layer of titanium (Ti), followed by a titanium nitride (TiN) barrier layer. Typically, silane-based oxide is deposited to form the dielectric. The oxide layer is then deposited, masked and etched. In those areas where MOM capacitors are not required, the oxide is etched away and down to the TiN barrier layer. During the removal of the photoresist layer defining the MOM capacitor, a portion of the TiN barrier oxidizes, which requires a deglaze (oxide removal) step prior to deposition of the top metal plate. Finally, the second metal layer, which may be aluminum (Al), copper (Cu), or aluminum copper alloy, such as AlCU(Si), is deposited to form the MOM capacitor.
A problem arises, however, during the oxide deglaze process in that the deglaze chemistry attacks the oxidized TiN barrier layer where it has been exposed. This causes the TiN barrier layer to erode in those exposed areas. The erosion of TiN material may be as much as 10 nm to 50 nm. The conventional solution to this problem has been to deposit a thicker TiN layer in order to compensate for this corrosive loss. However, a thicker metal/nitride layer increases the overall sheet resistance of the metal stackxe2x80x94an undesirable side effect. An additional problem results from this TiN layer erosion in that when the TiN layer is attacked, the silicon dopants, such as boron, phosphorus and arsenic, and titanium itself may diffuse through the eroded TiN barrier and into the upper or top metal layer. This diffusion can result in junction spiking. All of these problems result in reduced die yield, and increased manufacturing costs.
Additionally, while the titanium layer acts as a good adherent, it does, however, affect the subsequent grain size of the aluminum, aluminum/copper or aluminum/copper/silicon electrode layers of the contact plug. This, in turn, can reduce the conductivity of the aluminum stack layer.
Accordingly, what is needed in the art is a barrier material for MOM capacitors that addresses the deficiencies of the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device having a metal oxide metal (MOM) capacitor formed over a semiconductor wafer. In one embodiment, the device is a MOM capacitor that includes a first metal layer formed over the semiconductor wafer, a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, located on the first metal layer and an oxide layer located on the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). Additionally, the metal silicide can act as an etch stop for the etching process. The MOM capacitor is completed by a second metal layer that is located on the oxide layer.
In certain embodiments, the first metal layer may be titanium (Ti), but the first metal layer may also be a metal stack of titanium/titanium nitride (Ti/TiN), and in another embodiment, the oxide layer may be a silane-based oxide. The second metal layer may be an aluminum layer, an aluminum/copper alloy layer, an aluminum/copper/silicon stack layer or similar combinations of materials.
In another aspect, the present invention provides an integrated circuit formed on a semiconductor wafer. In one particular embodiment integrated circuit include a transistor, such as a comparable metal oxide semiconductor (CMOS) transistor that is formed on the semiconductor wafer and a MOM capacitor that is electrically connected to the transistor. The MOM capacitor includes a first metal layer located over the semiconductor wafer, a metal silicide layer located on the first metal layer, an oxide layer located on the metal silicide layer, and a second metal layer located on the oxide layer. The MOM capacitor may be formed in the same manner that the above-discussed embodiments are formed.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and broadest scope of the invention.